1. Field of the Invention
The present invention relates to a method for forming a conductive layer and, more particularly, to a method for forming a gate electrode or a metal line of a transistor in manufacturing a thin film transistor liquid crystal display (TFT-LCD).
2. Description of Related Art
For the manufacturing of a thin film transistor array, it is critical to control well the taper angle of a film because the tapers may affect the step-coverage of subsequently deposited films, the formation of voids, and the yield of TFT-LCDs.
The manufacturing of a TFT array mainly includes the steps of thin film deposition, photo-lithography, and etching, etc. for forming patterned conductive lines or gate electrodes. Currently, the taper angle is generally adjusted through regulating the parameters of the etching process, for example, use of particular etchant or gas to obtain a desired taper angle. Unfortunately, the taper angle formed by etching process usually cannot be controlled sufficiently to remain within the specification limits.
In recent years, in order to minimize the RC-delay, the materials with low electrical resistance, such as Al or Cu are increasingly used for forming metal lines of a TFT-LCD. Moreover, the multilayer structures are utilized to overcome the application limitation of Al and Cu as they can enhance the adhesion, reduce spiking issues, and avoid inter-layer diffusion. However, the difficulty of the etching step is consequently increased. As shown in FIGS. 1A and 1B, a multilayer metal structure, (for example, a metal structure of Ti/Cu/Ti) is formed on the surface of substrate 210. After being etched, the width of each layer is different from each other because each layer made of different materials has different etching rates. As shown in FIG. 1A, the middle layer 230 of the multilayer metal structure has a faster etching rate than the top and bottom layers so that the multilayer metal structure shrinks at its middle part after being etched. On the other hand, as shown in FIG. 1B, the middle layer 230 of the multilayer metal structure has a slower etching rate than the top and bottom layers so that the multilayer metal structure shrinks at its peripheral parts. Both the conditions mentioned above result in bad step coverage and occurrence of voids 250 during subsequent film deposition, such as deposition of a protecting layer 240. Although the issue of different etching rates does not happen in the single layer structure, the poor controlling of the etching process often causes a short circuit of metal lines and leads to inefficiency of devices. Furthermore, the operation channel may also be damaged during the etching process.
If the taper angle is defined as the included angle between the surfaces of deposited film and the substrate, it is usually larger than 60° after the deposited film has undergone the photolithography and etching processes in the prior art. However, the method for forming a conductive film of the present invention can form patterned conductive lines or a gate electrode that has a taper angle less than 60° when using photolithography, thin film deposition, and lifting-off of a photoresist. Consequently, a conductive film having a profile better than that of prior art is obtained, which increases the step-coverage of subsequent thin film deposition, reduces the occurrence of voids, simplifies the processing procedures, lowers the difficulty of processing, avoids the complex etching process, and achieves both high productivity and high yield.